The present invention is generally directed to the manufacture of semiconductors and, more particularly, to the manufacture of MOSFET (metal oxide semiconductor field effect transistor) devices.
It has been found that, in practice, the ability to scale known MOSFET structures and processes is complicated by numerous concerns and competing factors. Frequently, the need to develop a structural or process enhancement to solve a particular problem leads to the creation of other problems which previously had not been an issue. For example, halo implant doping is often used to provide a region of enhanced channel doping at the perimeter of the source-drain (S-D) diffusions (e.g., boron halos are often used around the N+S-D diffusions of NMOSFETs). In practice, however, the need for high channel doping (including high halo implant doping) to suppress short channel roll-off can lead to increased junction leakage, high junction capacitance, and hot-carrier degradation. As another example, the increasing need for dual work-function gate conductors can lead to additional process integration complexity (in order to avoid boron penetration through the gate insulator).
Still other issues are caused by the higher aspect ratios of the spaces between adjacent gate conductors which have more recently become increasingly desirable. The need for higher aspect ratios is driven by the higher gate conductor stacks, which are required to achieve a low sheet resistance, as well as constantly shrinking device dimensions. A high aspect ratio tends, however, to limit the ability to use angled S-D and halo implants, and also tends to complicate dielectric gap fill processes. To fill such high aspect ratio gaps, a reflow of dielectrics (such as borophospho-silicate glass or BPSG) is required. But such reflow tends to add to an already critical thermal budget, which in turn makes it necessary to contain the thermal budget to realize a scaling of doping profiles and also to avoid boron penetration through the gate insulator.
Still further complications are caused by difficulties in containing gate conductor sheet resistance because of the reduced cross-sectional area which is encountered. To reduce this gate conductor wiring resistance, higher level xe2x80x9cstitchedxe2x80x9d wiring is used (e.g., stitched wordlines). Stitched wiring tends to increase design complexity.
Therefore, the primary object of the present invention is to provide an improved structure and process for producing semiconductor devices, such as MOSFET""s, for purposes of reducing thermal budget and boron penetration concerns. Another object of the present invention is to reduce the aspect ratios which can be achieved, while maintaining a low sheet resistance. Still another object of the present invention is to provide an improved MOSFET channel structure which can implement such improvements. A still further object of the invention is to provide a MOSFET with improved electrical characteristics, including reduced short channel effect, lower junction capacitance, reduced junction leakage, and improved hot-carrier reliability.
These and other objects which will become apparent are achieved in accordance with the present invention by modifying the process for manufacturing semiconductor devices such as MOSFET""s to provide dual work-function doping following the customary gate sidewall oxidation step of the manufacturing process, greatly reducing thermal budget and boron penetration concerns. The concern of thermal budget (i.e., contributed to by BPSG dielectric reflow) is farther significantly reduced by a novel device structure which allows a reduced gap aspect ratio while maintaining low sheet resistance values. This reduced gap aspect ratio also relaxes the need for highly reflowable dielectric materials and also facilitates the use of angled S-D and halo implants, if desired.
Further provided is a novel structure and process for producing a MOSFET channel, lateral doping profile which suppresses short channel effects while providing low S-D junction capacitance and leakage, as well as immunity to hot-carrier effects. Yet another feature of the present invention is the potential for reduction in the contact stud-to-gate conductor capacitance, because the process of the present invention will allow a borderless contact to be formed with an oxide gate cap and oxide sidewall spacers.
An important feature of the process and the structures of the present invention is that the S-D junctions can be doped independently of the gate conductor doping which is performed. Such a process more easily allows the embodiment of N+gated p-type field effect transistors (PFET""s) and P+gated n-type field effect transistors (NFET""s), in addition to the standard N+gated NFET""s and P+gated PFET""s. Thus, the process and structures of the present invention achieve a variety of MOSFET structures. This flexibility is of significant value to product designers.